1. Field
Exemplary embodiments of the present invention relate to a latch circuit and a nonvolatile memory device including the latch circuit.
2. Description of the Related Art
An integrated circuit chip, such as a memory device, includes a latch circuit in order to maintain data for some time period.
FIG. 1 is a diagram showing a conventional latch circuit.
The latch circuit includes N latches 10_1˜10_N and a reset unit 20.
Each of the latches 10_1˜10_N latches data in response to a core voltage VCC supplied to a pull-up power supply node PUSPL_ND and a ground voltage VSS supplied to a pull-down power supply node PDSPL_ND.
The reset unit 20 resets the latches 10_1˜10_N to a low level when a 1st reset signal RESET is activated and resets the latches 10_1˜10_N to a high level when a 2nd reset signal SET is activated.
For the reset of the latches 10_1˜10_N to a low level, the 1st reset signal RESET is activated. The 1st transistors 21_1˜21_N of the reset unit 20 are turned on in response to the activated 1st reset signal RESET, and thus the 1st latch node Q of each of the latches 10_1˜10_N is grounded (VSS). Accordingly, the voltage level of the 1st latch node Q is lowered because of discharge of the 1st latch node Q. The voltage of each of the 2nd latch nodes Q_N of the latches 10_1˜10_N becomes a level of the core voltage VCC, and the voltage of the 1st latch node Q becomes a level of the ground voltage VSS. When the 1st reset signal RESET becomes a low level and thus the 1st transistors 21_1˜21_N are turned off, the 1st latch nodes Q of the latches 10_1˜10_N maintain voltage of a low level by the voltage of the pull-down power supply node PDSPL_ND and the 2nd latch nodes Q_N maintain voltage of a high level by the voltage of the pull-up power supply node PUSPL_ND.
For the reset of the latches 10_1˜10_N to a high level, the 2nd reset signal SET is activated. In this case, the operations of the latches 10_1˜10_N are opposite to those when the latches 10_1˜10_N are reset to a low level. The 2nd transistors 22_1˜22_N of the reset unit 20 are turned on in response to the activated 2nd reset signal SET, and thus the 2nd latch node Q_N of each of the latches 10_1˜10_N is grounded (VSS). Accordingly, the voltage level of the 2nd latch node Q_N is lowered because discharge of the 2nd latch node Q_N. The voltage of the 1st latch node Q becomes a level of the core voltage VCC, and the voltage of the 2nd latch node Q_N becomes a level of the ground voltage VSS. When the 2nd reset signal SET becomes a low level and thus the 2nd transistors 22_1˜22_N are turned off, the voltage of each of the 1st latch nodes Q of the latches 10_1˜10_N maintains a high level by the voltage of the pull-up power supply node PUSPL_ND, and the voltage of each of the 2nd latch nodes Q_N of the latches 10_1˜10_N maintains a low level by the voltage of the pull-down power supply node PDSPL_ND.
If a value stored in each of the latches 10_1˜10_N is different from a value to be reset, however, a lot of a current is consumed in order to reset the latches 10_1˜10_N. In particular, in a system including the latch circuit, an excessive peak current is induced due to the reset of latches.